components/tft/stmpe610.h@b74b0e4902c3 (annotated)
components/tft/stmpe610.h
Sat, 20 Oct 2018 13:23:15 +0200
- author
- Michiel Broek <mbroek@mbse.eu>
- date
- Sat, 20 Oct 2018 13:23:15 +0200
- changeset 0
- b74b0e4902c3
- permissions
- -rw-r--r--
Initial checkin brewboard
| 0 | 1 | /* |
| 2 | STMPE610 Touch controller constants | |
| 3 | */ | |
| 4 | ||
| 5 | #ifndef _STMPE610_H | |
| 6 | #define _STMPE610_H | |
| 7 | ||
| 8 | #include <stdint.h> | |
| 9 | ||
| 10 | #define STMPE610_SPI_MODE 1 | |
| 11 | ||
| 12 | // Identification registers | |
| 13 | #define STMPE610_REG_CHP_ID 0x00 // 16-bit | |
| 14 | #define STMPE610_REG_ID_VER 0x02 | |
| 15 | ||
| 16 | // System registers | |
| 17 | #define STMPE610_REG_SYS_CTRL1 0x03 | |
| 18 | #define STMPE610_REG_SYS_CTRL2 0x04 | |
| 19 | #define STMPE610_REG_SPI_CFG 0x08 | |
| 20 | ||
| 21 | // Interrupt control registers | |
| 22 | #define STMPE610_REG_INT_CTRL 0x09 | |
| 23 | #define STMPE610_REG_INT_EN 0x0A | |
| 24 | #define STMPE610_REG_INT_STA 0x0B | |
| 25 | #define STMPE610_REG_GPIO_INT_EN 0x0C | |
| 26 | #define STMPE610_REG_GPIO_INT_STA 0x0D | |
| 27 | #define STMPE610_REG_ADC_INT_EN 0x0E | |
| 28 | #define STMPE610_REG_ADC_INT_STA 0x0F | |
| 29 | ||
| 30 | // GPIO registers | |
| 31 | #define STMPE610_REG_GPIO_SET_PIN 0x10 | |
| 32 | #define STMPE610_REG_GPIO_CLR_PIN 0x11 | |
| 33 | #define STMPE610_REG_GPIO_MP_STA 0x12 | |
| 34 | #define STMPE610_REG_GPIO_DIR 0x13 | |
| 35 | #define STMPE610_REG_GPIO_ED 0x14 | |
| 36 | #define STMPE610_REG_GPIO_RE 0x15 | |
| 37 | #define STMPE610_REG_GPIO_FE 0x16 | |
| 38 | #define STMPE610_REG_GPIO_AF 0x17 | |
| 39 | ||
| 40 | // ADC registers | |
| 41 | #define STMPE610_REG_ADC_CTRL1 0x20 | |
| 42 | #define STMPE610_REG_ADC_CTRL2 0x21 | |
| 43 | #define STMPE610_REG_ADC_CAPT 0x22 | |
| 44 | #define STMPE610_REG_ADC_DATA_CH0 0x30 // 16-bit | |
| 45 | #define STMPE610_REG_ADC_DATA_CH1 0x32 // 16-bit | |
| 46 | #define STMPE610_REG_ADC_DATA_CH4 0x38 // 16-bit | |
| 47 | #define STMPE610_REG_ADC_DATA_CH5 0x3A // 16-bit | |
| 48 | #define STMPE610_REG_ADC_DATA_CH6 0x3C // 16-bit | |
| 49 | #define STMPE610_REG_ADC_DATA_CH7 0x3E // 16-bit | |
| 50 | ||
| 51 | // Touchscreen registers | |
| 52 | #define STMPE610_REG_TSC_CTRL 0x40 | |
| 53 | #define STMPE610_REG_TSC_CFG 0x41 | |
| 54 | #define STMPE610_REG_WDW_TR_X 0x42 // 16-bit | |
| 55 | #define STMPE610_REG_WDW_TR_Y 0x44 // 16-bit | |
| 56 | #define STMPE610_REG_WDW_BL_X 0x46 // 16-bit | |
| 57 | #define STMPE610_REG_WDW_BL_Y 0x48 // 16-bit | |
| 58 | #define STMPE610_REG_FIFO_TH 0x4A | |
| 59 | #define STMPE610_REG_FIFO_STA 0x4B | |
| 60 | #define STMPE610_REG_FIFO_SIZE 0x4C | |
| 61 | #define STMPE610_REG_TSC_DATA_X 0x4D // 16-bit | |
| 62 | #define STMPE610_REG_TSC_DATA_Y 0x4F // 16-bit | |
| 63 | #define STMPE610_REG_TSC_DATA_Z 0x51 | |
| 64 | #define STMPE610_REG_TSC_DATA_XYZ 0x52 // 32-bit | |
| 65 | #define STMPE610_REG_TSC_FRACT_XYZ 0x56 | |
| 66 | #define STMPE610_REG_TSC_DATA 0x57 | |
| 67 | #define STMPE610_REG_TSC_I_DRIVE 0x58 | |
| 68 | #define STMPE610_REG_TSC_SHIELD 0x59 | |
| 69 | ||
| 70 | ||
| 71 | #endif /* _STMPE610_H */ |
