Tue, 08 Oct 2019 12:00:31 +0200
Initial import of the CO2 meter application.
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Initial import of the CO2 meter application.
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1 | /* |
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2 | |
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3 | u8x8_d_ssd1325.c |
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4 | |
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5 | Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/) |
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6 | |
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7 | Copyright (c) 2016, olikraus@gmail.com |
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8 | All rights reserved. |
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9 | |
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10 | Redistribution and use in source and binary forms, with or without modification, |
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11 | are permitted provided that the following conditions are met: |
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12 | |
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13 | * Redistributions of source code must retain the above copyright notice, this list |
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14 | of conditions and the following disclaimer. |
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15 | |
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16 | * Redistributions in binary form must reproduce the above copyright notice, this |
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17 | list of conditions and the following disclaimer in the documentation and/or other |
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18 | materials provided with the distribution. |
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19 | |
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20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND |
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21 | CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
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22 | INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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23 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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24 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR |
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25 | CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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26 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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27 | NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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28 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
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30 | STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
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32 | ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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33 | |
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34 | SSD1325: |
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35 | 128 x 80, 16 Gray Scale Dot Matrix |
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36 | |
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37 | SSD0323: Identical to SSD1325, issue 720 |
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38 | |
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39 | |
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40 | */ |
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41 | |
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42 | |
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43 | #include "u8x8.h" |
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44 | |
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45 | |
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46 | |
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47 | static const uint8_t u8x8_d_ssd1325_128x64_nhd_powersave0_seq[] = { |
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48 | U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ |
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49 | U8X8_C(0x0af), /* display on */ |
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50 | U8X8_END_TRANSFER(), /* disable chip */ |
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51 | U8X8_END() /* end of sequence */ |
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52 | }; |
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53 | |
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54 | static const uint8_t u8x8_d_ssd1325_128x64_nhd_powersave1_seq[] = { |
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55 | U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ |
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56 | U8X8_C(0x0ae), /* display off */ |
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57 | U8X8_END_TRANSFER(), /* disable chip */ |
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58 | U8X8_END() /* end of sequence */ |
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59 | }; |
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60 | |
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61 | static const uint8_t u8x8_d_ssd1325_128x64_nhd_flip0_seq[] = { |
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62 | U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ |
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63 | U8X8_CA(0x0a0, 0x052), /* remap */ |
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64 | U8X8_END_TRANSFER(), /* disable chip */ |
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65 | U8X8_END() /* end of sequence */ |
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66 | }; |
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67 | |
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68 | static const uint8_t u8x8_d_ssd1325_128x64_nhd_flip1_seq[] = { |
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69 | U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ |
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70 | U8X8_CA(0x0a0, 0x041), /* remap */ |
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71 | U8X8_END_TRANSFER(), /* disable chip */ |
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72 | U8X8_END() /* end of sequence */ |
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73 | }; |
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74 | |
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75 | |
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76 | /* |
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77 | input: |
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78 | one tile (8 Bytes) |
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79 | output: |
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80 | Tile for SSD1325 (32 Bytes) |
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81 | */ |
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82 | |
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83 | static uint8_t u8x8_ssd1325_8to32_dest_buf[32]; |
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84 | |
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85 | static uint8_t *u8x8_ssd1325_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr) |
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86 | { |
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87 | uint8_t v; |
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88 | uint8_t a,b; |
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89 | uint8_t i, j; |
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90 | uint8_t *dest; |
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91 | |
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92 | for( j = 0; j < 4; j++ ) |
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93 | { |
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94 | dest = u8x8_ssd1325_8to32_dest_buf; |
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95 | dest += j; |
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96 | a =*ptr; |
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97 | ptr++; |
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98 | b = *ptr; |
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99 | ptr++; |
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100 | for( i = 0; i < 8; i++ ) |
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101 | { |
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102 | v = 0; |
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103 | if ( a&1 ) v |= 0xf0; |
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104 | if ( b&1 ) v |= 0x0f; |
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105 | *dest = v; |
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106 | dest+=4; |
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107 | a >>= 1; |
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108 | b >>= 1; |
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109 | } |
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110 | } |
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111 | |
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112 | return u8x8_ssd1325_8to32_dest_buf; |
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113 | } |
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114 | |
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115 | |
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116 | /*===================================================================*/ |
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117 | |
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118 | static uint8_t u8x8_d_ssd1325_128x64_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) |
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119 | { |
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120 | uint8_t x, y, c; |
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121 | uint8_t *ptr; |
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122 | switch(msg) |
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123 | { |
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124 | /* handled by the calling function |
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125 | case U8X8_MSG_DISPLAY_SETUP_MEMORY: |
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126 | u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1325_128x64_nhd_display_info); |
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127 | break; |
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128 | */ |
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129 | |
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130 | /* handled by the calling function |
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131 | case U8X8_MSG_DISPLAY_INIT: |
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132 | u8x8_d_helper_display_init(u8x8); |
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133 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_init_seq); |
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134 | break; |
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135 | */ |
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136 | case U8X8_MSG_DISPLAY_SET_POWER_SAVE: |
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137 | if ( arg_int == 0 ) |
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138 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_powersave0_seq); |
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139 | else |
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140 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_powersave1_seq); |
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141 | break; |
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142 | |
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143 | /* handled by the calling function |
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144 | case U8X8_MSG_DISPLAY_SET_FLIP_MODE: |
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145 | if ( arg_int == 0 ) |
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146 | { |
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147 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip0_seq); |
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148 | u8x8->x_offset = u8x8->display_info->default_x_offset; |
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149 | } |
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150 | else |
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151 | { |
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152 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip1_seq); |
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153 | u8x8->x_offset = u8x8->display_info->flipmode_x_offset; |
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154 | } |
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155 | break; |
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156 | */ |
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157 | #ifdef U8X8_WITH_SET_CONTRAST |
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158 | case U8X8_MSG_DISPLAY_SET_CONTRAST: |
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159 | u8x8_cad_StartTransfer(u8x8); |
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160 | u8x8_cad_SendCmd(u8x8, 0x081 ); |
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161 | u8x8_cad_SendArg(u8x8, arg_int ); /* ssd1325 has range from 0 to 255 */ |
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162 | u8x8_cad_EndTransfer(u8x8); |
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163 | break; |
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164 | #endif |
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165 | case U8X8_MSG_DISPLAY_DRAW_TILE: |
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166 | u8x8_cad_StartTransfer(u8x8); |
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167 | x = ((u8x8_tile_t *)arg_ptr)->x_pos; |
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168 | x *= 4; |
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169 | |
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170 | y = (((u8x8_tile_t *)arg_ptr)->y_pos); |
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171 | y *= 8; |
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172 | y += u8x8->x_offset; /* x_offset is used as y offset for the SSD1325 */ |
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173 | |
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174 | |
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175 | u8x8_cad_SendCmd(u8x8, 0x075 ); /* set row address */ |
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176 | u8x8_cad_SendArg(u8x8, y); |
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177 | u8x8_cad_SendArg(u8x8, y+7); |
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178 | |
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179 | do |
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180 | { |
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181 | c = ((u8x8_tile_t *)arg_ptr)->cnt; |
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182 | ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr; |
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183 | |
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184 | do |
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185 | { |
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186 | if ( ptr[0] | ptr[1] | ptr[2] | ptr[3] | ptr[4] | ptr[5] | ptr[6] | ptr[7] ) |
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187 | { |
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188 | /* draw the tile if pattern is not zero for all bytes */ |
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189 | u8x8_cad_SendCmd(u8x8, 0x015 ); /* set column address */ |
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190 | u8x8_cad_SendArg(u8x8, x ); /* start */ |
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191 | u8x8_cad_SendArg(u8x8, x+3 ); /* end */ |
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192 | |
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193 | |
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194 | |
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195 | u8x8_cad_SendData(u8x8, 32, u8x8_ssd1325_8to32(u8x8, ptr)); |
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196 | } |
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197 | else |
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198 | { |
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199 | /* tile is empty, use the graphics acceleration command */ |
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200 | u8x8_cad_SendCmd(u8x8, 0x024 ); // draw rectangle |
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201 | u8x8_cad_SendArg(u8x8, x ); |
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202 | u8x8_cad_SendArg(u8x8, y ); |
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203 | u8x8_cad_SendArg(u8x8, x+3 ); |
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204 | u8x8_cad_SendArg(u8x8, y+7 ); |
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205 | u8x8_cad_SendArg(u8x8, 0 ); // clear |
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206 | } |
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207 | ptr += 8; |
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208 | x += 4; |
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209 | c--; |
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210 | } while( c > 0 ); |
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211 | |
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212 | //x += 4; |
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213 | arg_int--; |
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214 | } while( arg_int > 0 ); |
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215 | |
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216 | u8x8_cad_SendCmd(u8x8, 0xe3); // no-op needs to be sent after last byte before cs is toggled. |
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217 | |
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218 | u8x8_cad_EndTransfer(u8x8); |
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219 | break; |
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220 | default: |
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221 | return 0; |
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222 | } |
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223 | return 1; |
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224 | } |
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225 | |
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226 | /*===================================================================*/ |
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227 | |
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228 | /* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */ |
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229 | static const uint8_t u8x8_d_ssd1325_128x64_nhd_init_seq[] = { |
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230 | |
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231 | U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ |
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232 | |
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233 | |
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234 | U8X8_C(0x0ae), /* display off */ |
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235 | U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */ |
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236 | U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */ |
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237 | U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */ |
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238 | U8X8_CA(0x0a1, 0x000), /* display start line */ |
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239 | U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */ |
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240 | U8X8_CA(0x0a0, 0x052), /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */ |
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241 | U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */ |
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242 | U8X8_C(0x0b8), /* set gray scale table */ |
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243 | U8X8_A(0x001), /* */ |
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244 | U8X8_A(0x011), /* */ |
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245 | U8X8_A(0x022), /* */ |
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246 | U8X8_A(0x032), /* */ |
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247 | U8X8_A(0x043), /* */ |
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248 | U8X8_A(0x054), /* */ |
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249 | U8X8_A(0x065), /* */ |
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250 | U8X8_A(0x076), /* */ |
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251 | |
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252 | U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128, Newhaven: 0x040 */ |
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253 | U8X8_CA(0x0b2, 0x051), /* frame frequency (row period) */ |
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254 | U8X8_CA(0x0b1, 0x055), /* phase length */ |
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255 | U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */ |
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256 | U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */ |
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257 | U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */ |
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258 | U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */ |
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259 | U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */ |
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260 | U8X8_C(0x0a4), /* normal display mode */ |
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261 | |
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262 | U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */ |
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263 | |
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264 | U8X8_END_TRANSFER(), /* disable chip */ |
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265 | U8X8_END() /* end of sequence */ |
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266 | }; |
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267 | |
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268 | static const u8x8_display_info_t u8x8_nhd_ssd1325_128x64_display_info = |
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269 | { |
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270 | /* chip_enable_level = */ 0, |
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271 | /* chip_disable_level = */ 1, |
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272 | |
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273 | /* post_chip_enable_wait_ns = */ 20, |
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274 | /* pre_chip_disable_wait_ns = */ 10, |
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275 | /* reset_pulse_width_ms = */ 100, |
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276 | /* post_reset_wait_ms = */ 100, /**/ |
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277 | /* sda_setup_time_ns = */ 100, /* SSD1325 */ |
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278 | /* sck_pulse_width_ns = */ 100, /* SSD1325 */ |
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279 | /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */ |
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280 | /* spi_mode = */ 0, /* active high, rising edge */ |
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281 | /* i2c_bus_clock_100kHz = */ 4, |
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282 | /* data_setup_time_ns = */ 40, |
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283 | /* write_pulse_width_ns = */ 60, /* SSD1325 */ |
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284 | /* tile_width = */ 16, |
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285 | /* tile_hight = */ 8, |
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286 | /* default_x_offset = */ 0, /* x_offset is used as y offset for the SSD1325 */ |
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287 | /* flipmode_x_offset = */ 8, /* x_offset is used as y offset for the SSD1325 */ |
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288 | /* pixel_width = */ 128, |
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289 | /* pixel_height = */ 64 |
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290 | }; |
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291 | |
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292 | uint8_t u8x8_d_ssd1325_nhd_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) |
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293 | { |
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294 | if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY ) |
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295 | { |
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296 | u8x8_d_helper_display_setup_memory(u8x8, &u8x8_nhd_ssd1325_128x64_display_info); |
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297 | return 1; |
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298 | } |
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299 | else if ( msg == U8X8_MSG_DISPLAY_INIT ) |
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300 | { |
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301 | u8x8_d_helper_display_init(u8x8); |
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302 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_init_seq); |
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303 | return 1; |
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304 | } |
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305 | else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE ) |
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306 | { |
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307 | if ( arg_int == 0 ) |
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308 | { |
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309 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip0_seq); |
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310 | u8x8->x_offset = u8x8->display_info->default_x_offset; |
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311 | } |
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312 | else |
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313 | { |
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314 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip1_seq); |
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315 | u8x8->x_offset = u8x8->display_info->flipmode_x_offset; |
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316 | } |
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317 | return 1; |
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318 | } |
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319 | return u8x8_d_ssd1325_128x64_generic(u8x8, msg, arg_int, arg_ptr); |
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320 | } |
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321 | |
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322 | /*===================================================================*/ |
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323 | /* OSRAM Pictiva 128x64 OLED */ |
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324 | /* https://github.com/olikraus/u8g2/issues/720 */ |
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325 | |
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326 | static const uint8_t u8x8_d_ssd0323_os128064_init_seq[] = { |
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327 | |
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328 | U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ |
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329 | U8X8_C(0x0ae), /* display off */ |
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330 | U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */ |
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331 | U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */ |
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332 | U8X8_CA(0x0a2, 0x040), /* display offset, shift mapping ram counter */ |
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333 | U8X8_CA(0x0a1, 0x000), /* display start line */ |
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334 | U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */ |
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335 | U8X8_CA(0x0a0, 0x052), /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */ |
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336 | U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */ |
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337 | U8X8_C(0x0b8), /* set gray scale table */ |
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338 | U8X8_A(0x001), /* */ |
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339 | U8X8_A(0x011), /* */ |
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340 | U8X8_A(0x022), /* */ |
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341 | U8X8_A(0x032), /* */ |
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342 | U8X8_A(0x043), /* */ |
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343 | U8X8_A(0x054), /* */ |
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344 | U8X8_A(0x065), /* */ |
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345 | U8X8_A(0x076), /* */ |
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346 | |
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347 | U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128, Newhaven: 0x040 */ |
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348 | U8X8_CA(0x0b2, 0x051), /* frame frequency (row period) */ |
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349 | U8X8_CA(0x0b1, 0x055), /* phase length */ |
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350 | U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */ |
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351 | U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */ |
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352 | U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */ |
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353 | U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */ |
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354 | U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */ |
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355 | U8X8_C(0x0a4), /* normal display mode */ |
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356 | |
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357 | U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */ |
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358 | |
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359 | U8X8_END_TRANSFER(), /* disable chip */ |
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360 | U8X8_END() /* end of sequence */ |
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361 | }; |
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362 | |
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363 | static const uint8_t u8x8_d_ssd0323_os128064_flip0_seq[] = { |
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364 | U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ |
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365 | U8X8_CA(0x0a0, 0x052), /* remap */ |
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366 | U8X8_CA(0x0a2, 0x040), /* display offset, shift mapping ram counter */ |
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367 | U8X8_END_TRANSFER(), /* disable chip */ |
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368 | U8X8_END() /* end of sequence */ |
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369 | }; |
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370 | |
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371 | static const uint8_t u8x8_d_ssd0323_os128064_flip1_seq[] = { |
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372 | U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ |
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373 | U8X8_CA(0x0a0, 0x041), /* remap */ |
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374 | U8X8_CA(0x0a2, 0x050), /* display offset, shift mapping ram counter */ |
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375 | U8X8_END_TRANSFER(), /* disable chip */ |
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376 | U8X8_END() /* end of sequence */ |
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377 | }; |
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378 | |
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379 | |
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380 | static const u8x8_display_info_t u8x8_ssd0323_os128064_display_info = |
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381 | { |
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382 | /* chip_enable_level = */ 0, |
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383 | /* chip_disable_level = */ 1, |
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384 | |
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385 | /* post_chip_enable_wait_ns = */ 20, |
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386 | /* pre_chip_disable_wait_ns = */ 10, |
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387 | /* reset_pulse_width_ms = */ 100, |
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388 | /* post_reset_wait_ms = */ 100, /**/ |
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389 | /* sda_setup_time_ns = */ 100, /* SSD1325 */ |
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390 | /* sck_pulse_width_ns = */ 100, /* SSD1325 */ |
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391 | /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */ |
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392 | /* spi_mode = */ 0, /* active high, rising edge */ |
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393 | /* i2c_bus_clock_100kHz = */ 4, |
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394 | /* data_setup_time_ns = */ 40, |
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395 | /* write_pulse_width_ns = */ 60, /* SSD1325 */ |
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396 | /* tile_width = */ 16, |
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397 | /* tile_hight = */ 8, |
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398 | /* default_x_offset = */ 0, /* x_offset is used as y offset for the SSD1325 */ |
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399 | /* flipmode_x_offset = */ 0, /* x_offset is used as y offset for the SSD1325 */ |
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400 | /* pixel_width = */ 128, |
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401 | /* pixel_height = */ 64 |
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402 | }; |
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403 | |
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404 | uint8_t u8x8_d_ssd0323_os128064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) |
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405 | { |
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406 | if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY ) |
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407 | { |
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408 | u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd0323_os128064_display_info); |
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409 | return 1; |
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410 | } |
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411 | else if ( msg == U8X8_MSG_DISPLAY_INIT ) |
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412 | { |
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413 | u8x8_d_helper_display_init(u8x8); |
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414 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_init_seq); |
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415 | return 1; |
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416 | } |
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417 | else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE ) |
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418 | { |
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419 | if ( arg_int == 0 ) |
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420 | { |
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421 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_flip0_seq); |
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422 | u8x8->x_offset = u8x8->display_info->default_x_offset; |
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423 | } |
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424 | else |
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425 | { |
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426 | u8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_flip1_seq); |
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427 | u8x8->x_offset = u8x8->display_info->flipmode_x_offset; |
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428 | } |
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429 | return 1; |
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430 | } |
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431 | return u8x8_d_ssd1325_128x64_generic(u8x8, msg, arg_int, arg_ptr); |
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432 | } |
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433 | |
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434 | |
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435 |