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comparison: components/u8g2/csrc/u8x8_d_ssd1329.c

components/u8g2/csrc/u8x8_d_ssd1329.c

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1 /*
2
3 u8x8_d_ssd1329.c
4
5 Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)
6
7 Copyright (c) 2016, olikraus@gmail.com
8 All rights reserved.
9
10 Redistribution and use in source and binary forms, with or without modification,
11 are permitted provided that the following conditions are met:
12
13 * Redistributions of source code must retain the above copyright notice, this list
14 of conditions and the following disclaimer.
15
16 * Redistributions in binary form must reproduce the above copyright notice, this
17 list of conditions and the following disclaimer in the documentation and/or other
18 materials provided with the distribution.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
34 */
35
36
37 #include "u8x8.h"
38
39
40
41 static const uint8_t u8x8_d_ssd1329_128x96_noname_init_seq[] = {
42
43 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
44
45
46 U8X8_C(0x0ae), /* display off */
47 U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
48 U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x03f * 1/64 duty - changed by CREESOO, acc. to datasheet, 100317*/
49 U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
50 U8X8_CA(0x0a1, 0x000), /* display start line */
51 U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
52 U8X8_CA(0x0a0, 0x052), /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */
53 U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
54 #ifdef removed
55 U8X8_C(0x0b8), /* set gray scale table */
56 U8X8_A(1), /* */
57 U8X8_A(5), /* */
58 U8X8_A(10), /* */
59 U8X8_A(14), /* */
60 U8X8_A(19), /* */
61 U8X8_A(23), /* */
62 U8X8_A(28), /* */
63 U8X8_A(32), /* */
64 U8X8_A(37), /* */
65 U8X8_A(41), /* */
66 U8X8_A(46), /* */
67 U8X8_A(50), /* */
68 U8X8_A(55), /* */
69 U8X8_A(59), /* */
70 U8X8_A(63), /* */
71 #endif
72
73 U8X8_C(0x0b7), /* set default gray scale table */
74
75 U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128 */
76 U8X8_CA(0x0b2, 0x051), /* frame frequency (row period) */
77 U8X8_CA(0x0b1, 0x055), /* phase length */
78 U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
79 U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
80 U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
81 U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
82 U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
83 U8X8_C(0x0a4), /* normal display mode */
84
85 U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */
86
87 U8X8_END_TRANSFER(), /* disable chip */
88 U8X8_END() /* end of sequence */
89 };
90
91 static const uint8_t u8x8_d_ssd1329_128x96_nhd_powersave0_seq[] = {
92 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
93 U8X8_C(0x0af), /* display on */
94 U8X8_END_TRANSFER(), /* disable chip */
95 U8X8_END() /* end of sequence */
96 };
97
98 static const uint8_t u8x8_d_ssd1329_128x96_nhd_powersave1_seq[] = {
99 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
100 U8X8_C(0x0ae), /* display off */
101 U8X8_END_TRANSFER(), /* disable chip */
102 U8X8_END() /* end of sequence */
103 };
104
105 static const uint8_t u8x8_d_ssd1329_128x96_nhd_flip0_seq[] = {
106 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
107 U8X8_CA(0x0a0, 0x052), /* remap */
108 U8X8_END_TRANSFER(), /* disable chip */
109 U8X8_END() /* end of sequence */
110 };
111
112 static const uint8_t u8x8_d_ssd1329_128x96_nhd_flip1_seq[] = {
113 U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
114 U8X8_CA(0x0a0, 0x041), /* remap */
115 U8X8_END_TRANSFER(), /* disable chip */
116 U8X8_END() /* end of sequence */
117 };
118
119
120 /*
121 input:
122 one tile (8 Bytes)
123 output:
124 Tile for ssd1329 (32 Bytes)
125 */
126
127 static uint8_t u8x8_ssd1329_8to32_dest_buf[32];
128
129 static uint8_t *u8x8_ssd1329_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)
130 {
131 uint8_t v;
132 uint8_t a,b;
133 uint8_t i, j;
134 uint8_t *dest;
135
136 for( j = 0; j < 4; j++ )
137 {
138 dest = u8x8_ssd1329_8to32_dest_buf;
139 dest += j;
140 a =*ptr;
141 ptr++;
142 b = *ptr;
143 ptr++;
144 for( i = 0; i < 8; i++ )
145 {
146 v = 0;
147 if ( a&1 ) v |= 0xf0;
148 if ( b&1 ) v |= 0x0f;
149 *dest = v;
150 dest+=4;
151 a >>= 1;
152 b >>= 1;
153 }
154 }
155
156 return u8x8_ssd1329_8to32_dest_buf;
157 }
158
159
160
161
162 static uint8_t u8x8_d_ssd1329_128x96_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
163 {
164 uint8_t x, y, c;
165 uint8_t *ptr;
166 switch(msg)
167 {
168 /* handled by the calling function
169 case U8X8_MSG_DISPLAY_SETUP_MEMORY:
170 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1329_128x96_nhd_display_info);
171 break;
172 */
173 case U8X8_MSG_DISPLAY_INIT:
174 u8x8_d_helper_display_init(u8x8);
175 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_noname_init_seq);
176 break;
177 case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
178 if ( arg_int == 0 )
179 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_powersave0_seq);
180 else
181 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_powersave1_seq);
182 break;
183 case U8X8_MSG_DISPLAY_SET_FLIP_MODE:
184 if ( arg_int == 0 )
185 {
186 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_flip0_seq);
187 u8x8->x_offset = u8x8->display_info->default_x_offset;
188 }
189 else
190 {
191 u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_flip1_seq);
192 u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
193 }
194 break;
195 #ifdef U8X8_WITH_SET_CONTRAST
196 case U8X8_MSG_DISPLAY_SET_CONTRAST:
197 u8x8_cad_StartTransfer(u8x8);
198 u8x8_cad_SendCmd(u8x8, 0x081 );
199 u8x8_cad_SendArg(u8x8, arg_int ); /* ssd1329 has range from 0 to 255 */
200 u8x8_cad_EndTransfer(u8x8);
201 break;
202 #endif
203 case U8X8_MSG_DISPLAY_DRAW_TILE:
204 u8x8_cad_StartTransfer(u8x8);
205 x = ((u8x8_tile_t *)arg_ptr)->x_pos;
206 x *= 4;
207
208 y = (((u8x8_tile_t *)arg_ptr)->y_pos);
209
210 y *= 8;
211 y += u8x8->x_offset; /* x_offset is used as y offset for the ssd1329 */
212
213
214 do
215 {
216 c = ((u8x8_tile_t *)arg_ptr)->cnt;
217 ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;
218
219 do
220 {
221 if ( ptr[0] | ptr[1] | ptr[2] | ptr[3] | ptr[4] | ptr[5] | ptr[6] | ptr[7] )
222 {
223 /* draw the tile if pattern is not zero for all bytes */
224 u8x8_cad_SendCmd(u8x8, 0x015 ); /* set column address */
225 u8x8_cad_SendArg(u8x8, x ); /* start */
226 u8x8_cad_SendArg(u8x8, x+3 ); /* end */
227
228 u8x8_cad_SendCmd(u8x8, 0x075 ); /* set row address */
229 u8x8_cad_SendArg(u8x8, y);
230 u8x8_cad_SendArg(u8x8, y+7);
231
232
233 u8x8_cad_SendData(u8x8, 32, u8x8_ssd1329_8to32(u8x8, ptr));
234 }
235 else
236 {
237 /* tile is empty, use the graphics acceleration command */
238 /* are this really available on the SSD1329??? */
239 u8x8_cad_SendCmd(u8x8, 0x024 ); // draw rectangle
240 u8x8_cad_SendArg(u8x8, x );
241 u8x8_cad_SendArg(u8x8, y );
242 u8x8_cad_SendArg(u8x8, x+3 );
243 u8x8_cad_SendArg(u8x8, y+7 );
244 u8x8_cad_SendArg(u8x8, 0 ); // clear
245 }
246 ptr += 8;
247 x += 4;
248 c--;
249 } while( c > 0 );
250
251 //x += 4;
252 arg_int--;
253 } while( arg_int > 0 );
254
255 u8x8_cad_EndTransfer(u8x8);
256 break;
257 default:
258 return 0;
259 }
260 return 1;
261 }
262
263
264 static const u8x8_display_info_t u8x8_ssd1329_128x96_display_info =
265 {
266 /* chip_enable_level = */ 0,
267 /* chip_disable_level = */ 1,
268
269 /* post_chip_enable_wait_ns = */ 20,
270 /* pre_chip_disable_wait_ns = */ 15,
271 /* reset_pulse_width_ms = */ 100,
272 /* post_reset_wait_ms = */ 100, /**/
273 /* sda_setup_time_ns = */ 100, /* ssd1329 */
274 /* sck_pulse_width_ns = */ 100, /* ssd1329 */
275 /* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
276 /* spi_mode = */ 0, /* active high, rising edge */
277 /* i2c_bus_clock_100kHz = */ 4,
278 /* data_setup_time_ns = */ 40,
279 /* write_pulse_width_ns = */ 60, /* ssd1329 */
280 /* tile_width = */ 16,
281 /* tile_hight = */ 12,
282 /* default_x_offset = */ 0, /* x_offset is used as y offset for the ssd1329 */
283 /* flipmode_x_offset = */ 0, /* x_offset is used as y offset for the ssd1329 */
284 /* pixel_width = */ 128,
285 /* pixel_height = */ 96
286 };
287
288 uint8_t u8x8_d_ssd1329_128x96_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
289 {
290 if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
291 {
292 u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1329_128x96_display_info);
293 return 1;
294 }
295 return u8x8_d_ssd1329_128x96_generic(u8x8, msg, arg_int, arg_ptr);
296 }
297
298

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